1.8V, 12-bit, 100MHz Pipelined ADC

In recent years, with the growth of the communications and multimedia market, the digital signal processing (DSP) technology which has also great developed and widely used in various fields. Using the DSP technology can achieve a variety of advanced adaptive algorithm which the analog circuit can't comply. Therefore, more and more analog signal processing technologies are being replaced by the DSP technology. It has the higher request of the analog-to-digital converter (ADC) which between analog system and digital system.In this thesis, a 12-bit, 1.8V, 100 MHz Pipelined A/D converters are introduced. Considering the trade off between speed, power dissipation and dynamic specification, the whole ADC is comprised of 11 stages, 1.5 bit per-stage, and a digital correction circuit eliminates errors between stages. Important blocks such as the Sample and Hold circuit are analyzed in detail. The dynamic comparator is adopted to eliminate the power dissipation, the large offset of the dynamic comparator can be eliminated by digital correction circuit. The operational-amplifier (OP) has designed according to the performance requirements of A/D converter, the gain, bandwidth and settling time.In the end, the A/D converter is implemented in TSMC 0.18μm CMOS process. In the Cadence software, the ADC circuit has been simulated and the layout has been designed. This ADC has already been completed and produced. The test results are mostly consistent with the design requirements.