VLSI Design Of2D IDCT Architecture Based On HEVC

HEVC (High Efficiency Video Coding) is a new generation of videocoding standard developed by ISO and ITU. The new standard is developedmainly for HDTV and systems of video capture. HEVC presented manynew coding tools and techniques, and its core objective is doubling thecompression rate based on the high profile of H.264/AVC. As HEVC codingstandard is improving steadily, the powerful hardware platform to support itwill also be developed. So studying its IDCT has great practicalsignificance.This paper introduces principle of IDCT in image compressiondecoding at first, analyzes and studies various fast algorithms of1D and2DDCT/IDCT, also summarizes the DCT/IDCT VLSI implementation whichhave been done by previous researchers. Than based on the algorithm ofHEVC IDCT, this paper presents a adaptive hardware implementationwhich is modular and easy to do Placement and Routing.In this design, row-column analyze is used to implementation the2DIDCT. To improve work frequency of the design, pipeline architecture and atranspose memory is used. Also to reduce the I/O peak bandwidth andhardware overhead, single-port I/O, the butterfly unrolling and theOdd/Even accumulation separation method is adopted. To avoiddisadvantages of the multiplier about slow speed and large area, shifter andadder are used instead of multiplier.At last, Pre-layout simulation, Logic synthesis and Placement&Routing for design has been done. Using TSMC90nm technology, the totalchip area is750×750um2, in which the SRAM area is2×430×111um2. Theresult shown that the proposed architecture is able to process 2560×1600@30fps image with32×32IDCT.