VLSI Design For The Key Module Of MPEG2 Decoder

Important modules of MPEG2 decoder are designed in this paper.In chapter2 a IDCT circuit based on dividing two dimensions transform into one dimension transform.which translates complicated transform into matrix multiplication of fixed coefficients which is esay to be implemented on hardware.In chapter3 a VLD circuit based on important word checking is designed. And then a IQ circuit of pipeline structure is designed in chapter4. The pipeline structure makes the outputs of IQ operation done only after a five periods delay. Last a appropriative system controller for MPEG2 decoder is designed in chapter5. VLD is a asymmetrical decoding process which make it difficult to output a result in one period.To settle this problem the paper designs a barrel shift fifo. There are two types of VLD circuit with different bus breadth..The VLD circuit with 8bit bus breadth is designed by FSM in this paper.To improve its rate,a pipeline structure can be introduced into the design. The last part of these chapters are function validate of circuit designed.The testing data is distilled from the normative MPEG2 data.By compare results of C and matlab with those of circuit designed.,the paper gets famous simulating results .