High Performance VLSI Architecture For HEVC Motion Estimation

Digital video services over network are expected to grow in terms ofresolution and quality, and the ultra-high definition television (UHDTV) isexpected to become available in the near future with larger screens, higherspatial/temporal resolution, etc. UHDTV needs huge delivery bandwidthfor carrying information. In order to reduce the bandwidth, the MPEG andVCEG have established JCT-VC team to develop the latest video codingstandard named HEVC(High Efficiency Video Coding), aiming to achievesimilar quality by using only half of the bit rate compared to H.264.HEVC brings in some new technology to achieve higher compressionrate. For motion estimation (ME), it employs the Largest Coding Unit (LCU)up to64×64pixels with Asymmetric Motion Partitions (AMP) and variablepartition depth (PD), which significantly increases the algorithmcomplexity of ME. And HEVC aims to larger video applications such asUHDTV.In this thesis, an effective VLSI architecture compatible to HEVC MEalgorithm is proposed for the first time. The architecture includes the globalcontroller, input data read-write module, SAD(Sum of Absolute Difference)generator and adder tree, larger PU SAD generator and RD cost withoutput modules. A hierarchy data reuse scheme and a memory accessstrategy are adopted to reduce off-chip bandwidth up to99.12%and toadjust to3search ranges (SR) including [-4,4),[-8,8) and [-16,16) pixels.By employing the SAD reuse strategy, the architecture supports full searchME with849different block sizes from4×4to64×64pixels, including168AMPs, such as4×16and24×32pixels. Moreover, the memory accessstrategy and partition of local memory reduce the memory area by50%. Using SMIC65nm technology, the proposed architecture issynthesized at the maximum work frequency of about330MHx with638KGates and power of295mW. Simulation results show that the architecture isable to process3840×2160p video at30fps at nearly280MHz.。...