The VLSI Architecture Design For The Entropy Encoder In H.265/HEVC

With the rapid development of the multimedia technology,the requirement for Ultra High Definition(UHD)video becomes stronger and stronger.The video resolution is moving towards 4K(3840 X 2160)and 8K(7680 X 4320).The high resolution,high frame rate and big bit depth result in a huge amount of data,which challenges the video coding technology.Aimed at the UHD video coding,the latest video coding standard,High Efficiency Video Coding(HEVC/H.265),was released in 2013.HEVC achieves a 50%bit-rate reduction for equal perceptual video quality compared to the former standard H.264/AVC.The coding complexity of HEVC also increases a lot,which challenges the UHD video real-time encoding.The entropy coding in HEVC is based on the CABAC(Context-based Adaptive Binary Arithmetic Coding)algorithm.CABAC involves high data dependencies in the context adaptation and interval division,which restricts the degree of pipelining and parallelism in the hardware implementation and makes CABAC a throughput bottleneck of the HEVC video encoders.This thesis focuses on the VLSI architecture design of HEVC entropy encoders.The main contributions are as follows.(1)A pipelined VLSI architecture for HEVC entropy encoders is proposed.The whole architecture consists of a Binarization And CtxIdx Calulation module,a Context Initialization module,a Context Storage And Updating module and a Binary Arithmetic Encoder(BAE).(2)A multi-bin parallel processing BAE architecture is proposed.This architecture adopts the state-of-art techniques in BAE design.Aimed at the complicated range updating process,this thesis proposes a Pre-Bitwise-NOT(PBN)technique and designs the corresponding Range Updating Unit.This thesis proposes an optimized Range Updating architecture and the corresponding assignment strategy,which could shorten the critical path of range updating and achieve a higher throughput.(3)A 4-bin parallel processing Context Storage And Updating module is designed.The context memory in the module is based on registers for a good timing performance.And the context memory supports the context initialization using a proposed Context Initialization module.This proposed VLSI architecture is implemented using Verilog HDL and synthesized under the SMIC 40nm CMOS technique using Synopsys Design Compiler.The synthesis results show that the proposed entropy encoder architecture could achieve a throughput of 1357Mbin/s,which could support the 8K@120fps UHD video real-time encoding.