Research On VLSI Structure And Implementation Of H.264 / HEVC Video Decoding

High Efficiency Video Coding (HEVC) is the latest video coding standard which is jointly developed by the two standardization organizations (MPEG and ITU). Its target is to reduce 50% bitrate in comparison with H.264/AVC under the same picture quality. In order to achieve this goal, many new coding tools are used in HEVC:the Quad-tree based picture partitioning, large size discrete cosine transform, discrete sine transform and new in-loop filter etc. These new algorithm greatly improve the coding efficiency of HEVC. But they also bring new challenges for the VLSI architecture of a video codec. Moreover, it will be a progressive process to replace the previous standards with new one. The new standard will coexists with traditional standards for quite a long time. There is also a vast demands for a universal video decoding architecture which can support multi-standard.In order to accommodate these requirements, several novel innovations and contributions are presented as the following:1. Various new algorithms in HEVC are evaluated in depth, which include CABAC, large size discrete cosine transform, discrete sine transform and new in-loop filter. A novel VLSI architecture is proposed for CABAC, which can support a shared storage of context models for both H.264 and HEVC. A unified VLSI architecture is proposed to support DCT with various transform size used in different standards. 4x4 DST can also supported in this architecture with little hardware overhead. A shared-SRAM architecture is proposed to support the new in-loop filter, which can greadly reduce the hardware cost.2. A 5-stage pipeline architecture is proposed to support the new picture partitioning for HEVC. The pipeline granularity is 32×32 pixel block. The macroblock with size of 16x16 is the basic unit of picture partitioning for traditional video coding standards. But the partition block size can be up to 64x64 in HEVC. A 32×32 pixel block granularity based pipeline architecture is proposed in this thesis. Each pipeline can process a block of size up to 32×32. This proposed architecture can reduce the hardware cost without compromising the system performance. And it is applicable to traditional standards as well as HEVC.3. An asynchronous pipeline is proposed to solve the bottleneck of entropy decoding block. Due to the serial feature of entropy decoding, Either CAVLC or CABAC will become the bottleneck of the whole system. The proposed asynchronous pipeline in this thesis can improve the throughput of entropy decoding block and reduce the power dissipation of the system.