VLSI Architecture Design And Implementation Of HEVC Transform

With the development of information technology,digital video services are expected to grow in terms of higher resolutions,higher frame rates and higher fidelity.High quality video service will generate a huge quantity of data which will be a heavy load on communication networks and data storage.In order to ease the burden on communication network,the Joint Collaborative Team on Video Coding of Moving Picture Experts Group and Video Coding Experts Group have developed the latest video coding standard called High Efficiency Video Coding(HEVC).HEVC standard introduces Integer DCT/IDCT with variable block size from 4× 4 to 32×32.Larger transform size means higher computational complexity.After the comparison of different mainstream VLSI architectures,two VLSI architectures for HEVC transform and inverse transform are proposed respectively in this dissertation.An even-odd decomposition algorithm is used to decompose the HEVC transform coefficient matrices of different size and reduce the computational complexity of the largest-size transform by 67%.Two unified VLSI architectures for N-point transform and inverse transform have been proposed respectively based on the even-odd decomposition algorithm.Addition and shift has been used to replace multiplication,and a Multiple Constant Multilication algorithm is adopted to reduce the number of shift and addition by 62% and 75% respectively.A VLSI architecture for two-dimensional transform which is based on the row-column decomposition algorithm with its tanspose buffer design is proposed at last.The proposed 2-D transform VLSI architectures are synthesized using GlobalFoundries 130nm process,the result shows the maximum operating frequency is 143MHz.The total gate counts for transform and inverse transform circuits are 388k and 392k respectively.The performance analysis shows that this VLSI architecture can support 7680×4320@60fps real time video encoding at 93.3MHz.