Data Flow Analysis And VLSI Architecture Design For HEVC Motion Estimation Module

The new generation digital video coding standard HEVC (HighEfficiency Video Coding) is published on Jan.26,2013. The object of thenew video coding standard is to double the compression rate while keepingthe same video quality. In order to achieve the designed compression rate,HEVC coding standard brings in many new features such as variable blocksize and quad-tree coding structure, etc. These new features make thecomputation of the HEVC coding standard more complex. The motionestimation is one of the module that consumes most of the computationresource in the coding standard. This thesis emphasis on the design speceexploration of the architecture for motion estimation module in HEVCcoding standard.The thesis begins from the motion estimation algorithm analysis. Thetraditional block-based motion estimation algorithm is adapted for HEVCvariable block size motion estimation calculation, and its data flow isexpanded and reformed hieratically. Then the hardware architecture model isproposed and a quantitative cost function is established between the dataflow and the architecture model. The data flow optimization is obtainedthrough minimize the cost function.One specific VLSI architecture is designed for the optimized data flow.The functional verification makes sure that the behavior of the architecture isidentical to the HEVC standard. The designed architecture is alsosynthesized by TSMC90nm technology, and its working frequency is about330MHz. The proposed architecture is able to support the HEVC4K×2K full high-resolution video coding in30fps.