VLSI Design Of DCT/IDCT IP Core Based On Image Processing Application

Discrete Cosine Transform and Inverse Discrete Cosine Transform are wildly used in coding and decoding of image processing. So far, it has adopted by many international standards like JPEG,MPEG1,MPEG2, MPEG4 and H26x etc. It's difficult to satisfy the requirement for real-time by software owing to its heavy quantity of computing. Therefore, we used to adopt hardware circuits to satisfy our requirement for speed in many practical applications. The content of the thesis researching is that hardware implementation of 8×8 2-D DCT/IDCT IP core for application of image processing. The thesis introduced principle and effect of DCT/IDCT in image processing at first, and further elaborated the advantages of DCT transform. And analyzed and studied various fast algorithms of DCT, summarized the working for DCT fast algorithms and its VLSI implementation which has done by previous researchers. Based on characteristics of image process and IP design idea, combining DCT fast algorithms and hardware implementation, on the purpose of improving speed and decreasing area and power, the thesis presented a way of DCT/IDCT hardware implementation. The way adopted pipeline architecture and changed 2-D DCT/IDCT to two 1-D DCT/IDCT based on characteristic of row-column decomposition. In the design of 1-D DCT/IDCT, since we knew the value of DCT cosine coefficients, by making use of its rotation characteristic, multiplication function can be designed by shift and addition logic instead of direct multiplication unit by which can save design resources while improve the speed. At last, synthesize and verification for design has been done. The result shown that the design could complete the function of 8×8DCT or IDCT under 100M clock frequency. Except 64×15RAM which design needed, other logic area is about 55477.90625um after synthesis by 0.35 technology library.