HEVC IDCT/IDST VLSI Architecture For UHDTV

Video and Internet technology has been rapidly developing in recentyears. Higher resolution and lower bit rate will be the trend in video codec.As H.264/AVC will soon become a bottleneck of video compression, thenewest video compression standard HEVC(High Efficient Video Coding)is developed by VCEG and MPEG.The main goal of this new standard is to achive50%bit rate reductionfor equal quality. To achive the improvement, variable transform block sizefrom4×4to32×32for DCT/IDCT as well as mode dependent4×4pointIDST is supported in HEVC, which makes the transform core harder todesign.We have a research on the architecture for1D and2D IDCT at first.Then analyzes and summarizes the implementation in previous work. Byanalizing transform data of reference video sequence provided by JCT-VC,we propose an area and throughput efficient2D IDCT/IDST VLSIarchitecture which is different from traditional parallel butterflyarchitecture. Two1D IDCT transform core and single I/O port structure areused to implement a2D IDCT. Through data flow scheduling and highlyoptimized Constant Multipler Array(CMA) structure, the architecture cansupport variable size of IDCT transform from4×4to32×32as well as4×4IDST. A dynamic allocation algorithm for SRAM based transpose bufferstratagy is also proposed based on the architecture proposed in this paper.By using this algorithm, the transpose buffer can deal with variable blocksize transform without any pipeline stall.The architecture is implemented using SMIC65nm1P9M technologylibrary. The results show that the hardware cost of1D transform core is about40.1K gate count with maximum frequency of500MHz. Comparedwith previous work, our design achieves36%reduction in hardware costand66%improvement in throughput efficiency. The chip area is930.4×928.8um2and the power is145.3mW. Experimental results showthat our design can support real-time4K×2K@30fps video sequence at412MHz to fulfill UHDTV applications.