Design Of 65nm High Speed SRAM For Cache

Static random access memory(SRAM) is widely used in SoC. High performance computing systems need high SRAM performance. With development of process, random disturbances with high leakage make SRAM design belt to great challenges.In this paper, SRAM speed is key, power and stability are premise, with 8T cell based on SMIC 65 nm process, a 1024Words×32Bits SRAM is designed. Simulation results show in worst corner, average access time is 0.9003 ns, average power is 39.44uW/MHz in TT corner, and layout area is298.0 um. Compared with the SMIC 65 nm high performance memory compiler generated 6T SRAM, this design improves speed of 19.16%, the leakage reduction of 12.82%. The circuit is built on Cadence Virtuoso, Hspice is used to perform module functional simulation, Finesim to do whole circuit simulation. Layout is drawn with Laker.The main content and research object of is: Firstly, read and write separated 8T cell is brought. They are optimized. Simulations show 8T cell has advantages in stability and speed. In cell array, blocking impacts for speed and power is studied, eight sub-arrays is adopted. Secondly, hierarchical decoder is studied. With logical efforts, its size is manually optimized. Eventually, skewed gate as wordline driver is optimized. Thirdly, multi-threshold transistor speed and leakage is studied, LVT transistors are used in cell devices and peripheral circuits. Timing circuit is concerned, clock input with feedback circuit, write timing circuit based on detect circuit, read timing circuit based on replica cell are optimized. Clock order is optimized and efficiency is improved.