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Design Of 2.6-5GHz Pulse-Swallow Counter For Ultra Wideband Millimeter-wave Frequency Synthesizer

Posted on:2019-04-03Degree:MasterType:Thesis
Country:ChinaCandidate:M M SunFull Text:PDF
GTID:2428330590975487Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of wireless communication technology and the continuous improvement of human communication requirements for high-speed short-distance communication,the communication technology applied to the millimeter-wave frequency band has become a research hotspot in recent years and has great potential for development.Frequency divider is a key module in phase-locked loop(PLL)-based millimeter-wave frequency sources.The divider is the key to a millimeter-wave frequency source that can provide multiple high-precision frequency signals while realize high frequency and low power consumption.The performance of the frequency divider largely determines the overall performance of the millimeter wave frequency source.Therefore,designing a programmable divider with high speed and low power consumption has important research significance and practical value.This thesis designs a Pulse Swallow(P/S)counter for high-speed programmable integer divider based on 0.13?m SiGe BiCMOS process.The operating frequency of this P/S counter is 2.6-5GHz,where the P counter has a count range of 30-50 and the S counter has a range of 0-7.Both the P and S counters use an asynchronous cascaded binary subtraction-counting architecture,which significantly reduces the circuit design complexity and clock signal load compared to the synchronous circuit architecture,while further reducing the power consumption of the circuit.The P and S counters use a simplified True Single Phase Clock D flip-flop with a reset function.At the same time,the state detection circuit consists of embedded nor-gate TSPC D flip-floP/S,and the delay of the P and S counters from the counting end state to the next counting starting state is reduced.So the overall working speed of the P/S counter is improved.The operating voltage of the P/S counter is 1.8V.Simulation of electromagnetic field mixing shows that within the range of-55?C to 125?C of the TT,FF and SS corners,the P/S counters are all able to work correctly at different count values in the 2-5 GHz band.The P/S counter has a power consumption of 6.3mW and a chip area of 1.2×0.5mm~2.Therefore,the P/S counter designed in this thesis has the advantages of high operating frequency,wide frequency division ratio,low power consumption and etc.In addition to being applied to ultra-wideband millimeter wave frequency source system,the P/S counter can also be applied to other Millimeter-wave Frequency Synthesizer chiP/S after been slightly modified.
Keywords/Search Tags:Integer programmable divider, P-S counter, TSPC D flip-flop, SiGe BiCMOS process
PDF Full Text Request
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