A BIST Design Method For3D Chips

With the development of the semiconductor industry, the performance of chipsis stronger than ever. At the same time, chips with high-speed and high-integrationtake severe challenges to the test. Due to the increasing chips’ integration, it ismore difficult and more expensive to use the external test equipments, thispromotes the application of BIST, which has been widely accepted to be thepreferred method in the testability methods.In nanometer era, chips are now more integrated and the feature size is gettingsmaller and smaller. But it is more difficult to enhance the circuit’s integration byreducing the transistor’s size or shorting the length of interconnection lines. Inorder to break the existing physical and material limitations in the integrated circuitdevelopment, we need to find a new method or structure. It is against thisbackground that the three-dimensional integrated circuits(3D-IC) comes to us, itprovides a new technology to break the bottleneck. Three-dimensional chips aredifferent from the planar chips, It stacks some dies through TSVs(Through SiliconVias). This vertical integration will make chips smaller and make chips’performance higher.This thesis studies the benefits of three-dimensional integrated circuits and thechallenges in the3D chip testing. Combined with the existing3D chip test methods,this thesis proposed a built-in self test(BIST) design method─3DC-BIST(3DCircuit-BIST) which based on the hierarchical architecture. This method designedthe BIST structure for each non-bottom circuits’ pre-bonding tests and the BISTstructure for the overall circuits’ post-bonding tests, then increased the adjustedstructure into the BIST, so the BIST not only test the bottom circuits beforebonding, but also test the overall circuits after bonding. This thesis Presents a BISTstructure for3D chips, and reduced the overhead in area comparing to thetraditional methods. Experimental results showed that our method can achieve thesame fault coverage compared to the traditional3D BIST method. The averagesurface cost of3D chip is reduced by6.41%compared to the traditional3D BISTmethod.