The Research Of BIST Test Vector Generation For I_DDT Testing

IC testing technology is the key of producing high-performance integrated circuits. Due to the diversity of the faults and manufacturing defects in CMOS IC, some of the faults can neither be defected by voltage test nor by IDDQ test. In the middle of 1990's, the concept of IDDT test is proposed .The test attempts to observe and analysis the transient currents during the logical change of the circuit to detect some fault that can not be detected by voltage test and IDDQ test and improve product quality.Along with the development of modern design and packaging technology, external test can't meet the needs. On one hand, external test need specialized testing tools, on the other hand, the generation of vectors is difficult.the number of vectors in the test set is excessive and the test time is long. BIST gradually gains reputation because of its effectiveness and quickness.According to existing research results, most testing pairs in IDDT test only have one or two different bits.In this page a BIST test vector generator used for IDDT test is designed.This generator generates the first vector in the IDDT testing pair randomly and the second one is generated by changing one or two bits of the first vector randomly.Then the two vectors composing a testing pair is imposed to the CUT.The experimental results show that this method can obtain much higher fault coverage by using much less test vectors.As IDDT test needs a testing pair,the BIST method used for IDDT test have proposed.All have such problems as long test vectors and big test time cost. This paper designs a new BIST method for IDDT test on the basis of analying the character of IDDT test vectors, this method changes the test pair used for IDDT test into a one-dimensional vector and generates using multiphase BIST and then changes the one-dimensional vector into a test pair which is needed in the IDDT test and finally imposes the test pair to the CUT.The experimental results show that for the circuits having many inputs,the length of test vectors generated by this method is much shorter and the hardware cost is smaller.