Research On Techniques Of Vield And Testing Costs For Three Dimensional Chips

The three-dimensional integrated circuit(3D IC)by vertically stacking multiple chips,can greatly enhance the integration of transistors,and it is considered to be an important technology to continue Moore’s Law.However,various types of TSV defects can be introduced during the process of manufacturing,thinning and bonding,and the faulty TSVs often tend to be clustered together,making the yield of 3D ICs much lower than expected.At the same time,the process of 3D IC testing is complex,and some ICs have to be discarded because of failed bonding,thus the cost for 3D IC testing is relatively high.Aiming at the above problems,we will solve the yield problem by TSV testing and redundancy.The TSV testing is conducted at the pre-bond stage,and then faulty TSVs will be screened out,and then the yield loss caused by indroucing faulty TSVs into the 3D ICs will be shorten,enhacing the yield of 3D ICs.At the same time,redundant TSVs are inserted to tolerant faulty TSVs,especially those who are clustered together,and the enhancement of 3D IC yield can be realized by TSV redundancy.As for the test cost problem,we consider to optimize the stacking order during mid-bond stage,reducing the test costs.The main contributions of the dissertation are as follows:(1)Vernier-ring based pre-bond TSV testing.TSV faults are often shown as delay faults,faulty TSVs can lead to TSV network transmission variation,compared with those TSVs who are fault-free.This dissertation applies the vernier method in TSV delay deviation testing,the two ring-type vernier delay lines are connected with fault-free TSV and TSV under test.Whether the TSV under test is faulty can be determinered by detecting the delay vartion between these two delay lines via the proposed vernier-ring method,and this delay vartion can be quantizatied to digital code for output,which can reflect the degree of faulty TSVs.The simulation results show that this method can achieve the detection accuracy as high as 10ps,can it can effectively detect small delay TSV faults.(2)Region-based TSV repair method for clustered faults.The TSV array is evenly divided into four regions,and redundant TSVs are inserted into different regions respectively,when the clustered TSV faults occur,each region will search repair paths from faulty TSVs to redundant TSVs,achieving the TSV clustered faults tolerance.The simulation results show that for the given 8*8 TSV array,the proposed method can achieve yield to be 99.88%,the repair rate can be improved by 30.84%,and the timing overhead can achieve a reduction of 11.27%-20.79%.(3)A stacking reordering method for mid-bond test cost reduction.Different from the previous test cost model,this method mot only considers test time,but also considers the impact of the discarding costs caused by failed bonding on the total test costs.This method can decrease the discared costs by chaning the stacking order,and the chips with higher tendency to fail are arranged at the bottom for preferential stacking.At the same time,the TAM(test access mechanism)bandwidth,the TSV number and the tets power are optimized to minimize the test time for the determined stacking order.The experimental results show that compared with the two baselines:pyramid and inverted pyramid sequential order,the test costs of the proposed method can be reduced by 12.92%-13.71% and 61.66%-63.09%,respevtively.