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Design And Implementation Of Key Modules And SoC For H.264/AVC Encoder

Posted on:2013-05-10Degree:MasterType:Thesis
Country:ChinaCandidate:B C LiFull Text:PDF
GTID:2248330377960910Subject:Detection Technology and Automation
Abstract/Summary:
With the rising of intellectual mobile terminal devices in the age of Mobile internet, the chip design, especially portable multimedia products, is actually facing the unprecedented opportunity and challenge. In order to fit the development trend of multimedia processing chips, this dissertation study entropy, motion vector prediction in H.264/AVC and SoC design method of codec. Based on the study the dissertation uses a dedicated hardware solution which is based on H.264and SoC technologies. Experiments show that this dissertation get an obvious rise of throughput rate using less hardware source based on some new technologies. Besides, the SoC system was implemented into a FPGA based development board on the SoPC design platform. The main work of the dissertation is as following:1, this dissertation proposed a new hardware method of CAVLC scanning which make the CAVLC encoder get an rise of throughput rate without using the method of increasing parallelism, the experiment results show that this method reduce the scanning time obviously.2, having achieved the RTL design of code processing unit which is the key module of H.264/AVC encoder; having built the encoder SoC system using code processing unit and design of system software, having accomplish the function aim of the SoC system.3, implementing the encoder system on FPGA whose type is stratix III EP3SL340F1760C4, the implementation result of640x480version showing the design meet the real-time need of25f/s.
Keywords/Search Tags:SoC, H.264/AVC, entropy, CAVLC, FPGA
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