The Design And FPGA Implementation Of H.264 Entropy Decoder

H.264 video standard is used in many consumer electronics,including:MP4,mobile phones,television,digital television and so on.The context-based adaptive variable length coding(CAVLC) and Columbus coding are two entropy coding methods used by H.264.CAVLC introduces the context model.Because the pixel residual has been encoded according to the pixel residual that has been encoded, the compression ratio is futher improved. With this improvement,the decoding complexity of H.264 entropy coding has been further enhanced than the MPEG-4 video standard. In the case of high-definition video sequence decoding, the software decoder can no longer meet the requirements of real-time.So, hardware architecture of H.264 entropy decoder and its FPGA implementation is proposed in this paper.The major contribution is as following:(1) The overall structure of the entropy decoder: In this paper,the auxiliary header information decoding module(Including the sequence parameter set, picture parameter set, as amended to take the lead, stripe data, part of the macro block layer parameters, residual motion vector decoding) and pixel residuals decoding module are introduced in turn. The auxiliary header information decoding module mainly relys on Columbus decoding module in decoding process.The pixel residuals decoding module relys on CAVLC decoding module. By the top-level control module,a complete entropy decoder module is built.(2) The optimization and research of important modules: The pipeline control module is introduced into the CAVLC decoder. Through the rational allocation of the clock, when decodes I frame of whose quantization coefficient is 28,the CAVLC decoder decodes each macroblock consuming 350 clock cycles.In the decoding process of element "coeff_token", the high-frequency and low-frequency code words are separated to deal with.The high-frequency code words are decoded by combinational logic.The low-frequency code words are stored in memory to decode. A new memory organization strategy is proposed to reduce the memory consumption of low-frequency code words. The method of creating address by code words is improved. The memory consumption is reduced by the new memory organization strategy.(3) Hardware architecture of H.264 entropy decoder and its FPGA implementation:The whole design uses Verilog HDL language to describe and Modelsim sofeware to simulate. By comparing the result of Modelsim and JM (reference software decoder), the simulation work of the entropy encoder is completed. The entropy decoder has been integrated into a H.264 decoder,and the complete H.264 decoder works properly. The FPGA is Altera's Stratix II EP2S180 type chip. After the simulation of the entire H.264 decoder, the whole H.264 decoder is downloaded to FPGA chip.Through the display as the output display device, the whole H.264 decoder achieves the normal decoding.The max frequency of the entropy decoder can achieve to 123MHZ when it is synthesized alone. When the frequency can reach 100MHZ, according to the average clock cycle,the entropy decoder can meet the demond of the video sequence whose resolution is 1920x1088, and frame rate is 30fps, and quantization coefficient is 28.