Fpga Implementation Of The H.264 Baseline Profile Entropy Encoder

With the development of microelectronics and communication engineering, the video codec technology has advanced significantly. The improvement promote the progress of industry and technique, form PAL and NTSC to high define standard. The quality of video has leaped than ever before and with it the great challenge of video codec. The pre video standard can perform high define codec, but it is not design for such condition, there need a new one.The specification of the paper1 The overviewIn this part, the paper introduces the foundation of video codec, and then specifies the standard of H.264/AVC.2 the analyze of the algorithmicThe paper bases on the software algorithmic. In the first part, there introduce the software dataflow and analyses its character, and then specify the VLC and CAVLC core union in detail, focus on its principal of algorithmic.3 The hardware structure design and verificationBase on software algorithmic and the characteristics of hardware, the paper proposes a implementation of the VLC hardware structure, especially the core union and relative inter design's structure. The design is implemented by verilog, and verified in MODELSIM.4 The hardware implementationThe hardware union includes data process and control parts, UVLC include exp coulomb, stream combine, syntax element register file and state machine. The CAVLC include core union and state machine.The design is impement by ISE, and it includes 5208 slices and 2674 register, which can reach 100Mhz frequence.5 Hardware platformsIn this part introduces the implementation platform, including the connection of DSP and FPGA, the EMIF bus and is specification.