VLSI Structure Design Of CAVLC Encoder In H.264

The rapid development of digital technology has brought human into a brand-new digital and information society. The popularity of digital multimedia products is benefited from the progress of video compression technology, especially the new research development of the newest generation video coding standard一H.264standard. Meanwhile, abiding by Moore’s Law, the rapid development of semiconductors and information technology laid the hardware basis for the real-time application with complex encoding algorithms.As the key technologies in H.264, Entropy coding based on the statistical properties of stochastic processes, is realized by statistic information, reducing coding redundancy, further improving the compression efficiency.This paper mainly researches on CAVLC entropy coding in H.264baseline profile and extended profile. Comparing with CABAC, CAVLC algorithm is simple to understand, easy to achieve in the case of low complexity, time-critical environment and certain hardware constraints.However, it is difficult to meet real-time requirements of high-definition video encoding in CAVLC.this paper puts forward a thorough stucy in CAVLC algorithm and presents an efficient CAVLC encoder based on hardware architecture.This paper briefly describes the history development of video coding standard and a comparison of several coding standards, and then focuses on the codec framework and key technologies of H.264.Then it makes a detailed study and analysis of CAVLC algorithm, and presents an efficient CAVLC encoder in hardware architecture, further it describes main modules of the CAVLC encoder architecture in detail.Finally, the introduction of the CAVLC encoder design verification methods is given, and simulation and synthesis performance show that the proposed CAVLC encoder hardware architecture can meet the HD(1920×1080＠30f) real-time video encoding.