Special Chip Integration, Design For Testability

With the sharp development of LSI and VLSI, the integration of chip gets denser and denser. But the extra ports for testing is limited and test is more difficult than before. We even must spend more time and money on chip testing rather than chip design. In order to allay the difficulty of test, one should pay attention to the Design For Testing (i.e. DFT) during the period of system design. In the process of system developing, the engineer should first solve the problem of DFT, especially when lots of digital circuits or IP cores are used in System On Chip. The ratio of fault covering has always been the focus of testing designer in DFT for a long time. Now a single chip contains all kinds of circuits, so to solve the problem of the ratio of fault covering is even harder than before. A sound DFT not only has a high ratio of fault covering but also occupies little area of a chip in order to lower the usage of sources. From the view point of the foundation of DFT (which includes the testable measure of gate-level circuits, the testable and controllable measure of functional-level, the flow and methodology of DFT and so on), the author introduce some common testing technology such as scan and BIST in modern times. Especially the Boundary Scan Technology has been widely adopted in the DFT of VLSI. With the special controller, the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports, and the response could also be shifted to the testing output ports. BIST is an efficient solution for the testing of SOC. It is built up with prompting and responding circuits and these two parts are added to the circuit being tested so that the engineer need not consider the testing vector, for it's generated automatically. Furthermore, the author also discussed the DFT of SSX01 (which is a kind of cipher chip) and compared all kinds of testing solutions, finally presented the DFT of the module of ROM and operation core...