Study And Implementation Of LDPC Encoder And Decoder In DVB-S2

Based on DVB-S2LDPC (Low-Density-Parity-Check) code, thispaper has researched features of DVB-S2LDPC encoding and has analyzed theperformance of different LDPC (Low-Density-Parity-Check) decoding algorithm. Interms of the simplify of check-node update, decoding algorithm can be sorted to BP,min-sum, modified mim-sum and line approximation; In terms of updating order, itcan also be sorted to SMP(Standard Message Passing, a parallel scheduling) andLMP (Layered Message Passing,a serial scheduling including Row Message Passingand Column Message Passing). In the hardware realization, the encoder has fully usethe resources of FPGA.104units of computing parity address and parity data bit,which architecture have five grades of pipeline and832dual-port1x1024RAMwhich is dynamically configurable are used to achieve fully utilization of resourceand optimization of throughput. The number of dual-port RAM can be confuguredaccording to the code rate for approving the throughput per clock cycle. The encodersupport parallel processing of1bit,2bit,4bit,8bit bch data which consumes3279logic elements,792registers and854923bits memory, the throughput of it is up to800Mbps when the clock frequency is100MHz. A LDPC decoder for the codelength16200and code rate0.6is designed in DVB-S2which is based on SMP offsetmin-sum algorithm. The decoder consumes24004logic elements,6437registers and448594bits memory. Working on the highest clock frequency of398MHz, itachieves the throughput of289Mbps. The comparasion result with other designsshows that scheme proposed improves the decoder’s throughput as well as reducedthe hardware resource consumed effectively.We have realized encoder and decoderof the DVB-S2LDPC code whose rate is3/5and length is16200. The decoder isbased on SMP offset min-sum algorithm.After our study, we can conclude that: The structure of decoder using sharedmemory banks and writing the LLR (Log-Likelihood Ratio) back to the RAM haslow area and high throughput. After all, this paper has offered a way to choose decoding scheduling to adapt todifferent demands and aims to decrease the resource usage of FPGA while improvethe throughput of decoder.