Design And FPGA Implementation Of Complexity Reduced LDPC-CC Decoder Based On Compact Decoding Architecture

In a wireless communication system,the transmission of information will be interfered by channel noise,which will cause errors of information.Therefore,it is important to adopt effective techniques to resist the interference caused by noise,the channel codes come out as the times require.Low-density parity-check convolutional codes(LDPCCC)was proposed in 1999 as low-density parity-check(LDPC)codes with convolutional characteristics.In recent years,it has attracted the attention of many scholars due to its unique encoding and decoding characteristics.This thesis will use a combination way of theory and simulation to study and improve LDPC-CC,and finally complete the hardware design and implementation of the proposed decoder in this thesis.This thesis first studies the definition and characteristics of LDPC-CC,including sparse check matrix and Tanner graph.Then,the syndrome former encoder and partial syndrome former encoder of LDPC-CC are deduced and analyzed in detail,which leads to the research on the end of the encoding.Finally,the importance of tail bits in data frame transmission scenarios is fully researched,and the end of encoding is deduced.In terms of decoding,this thesis first studies the traditional pipeline decoding algorithm,and the computational complexity,storage requirements and the initial delay of decoding are analyzed and calculated.On this basis,different ideas of improved decoding are researched,including on-demand variable node activation(OVA),stopping rule and compact pipeline decoding structure.Research has found that although these decoding algorithms are improved compared to traditional decoding algorithms,there is still room for further optimization.Therefore,this thesis proposes an improved LDPC-CC decoder design,the basic idea is based on the compact decoding structure,and appropriate weighting factors and stopping rules are added to each decoding processor.The results show that the proposed decoder is superior to the traditional pipeline decoder in terms of decoding performance,computational complexity and storage requirements.In addition,the thesis also simulates and analyzes the bit error rate(BER)performance of LDPC-CC on different iteration times,code length,weight factors,end of encoding and decoding algorithms.After the detailed analysis and research of the decoder,the thesis finally completes the hardware design and implementation of the proposed LDPC-CC decoder.First,on the Quartus II software platform,verilog hardware description language(HDL)is used to implement the decoder module from the top-down way,which mainly includes the stopping rule module,variable node update module,check node update module and control module.Then Modem Sim is adopted to simulate the function and timing of the designed project,and the hardware resource consumption is also analyzed.Finally,the Power Play Early Power Estimator tool is used to test the power consumption of the designed decoder at different frequencies.