Decoding Research Based On Majority-Logic Algorithms For NB-LDPC Code And FPGA Implementation

Nowadays with the rapid development of the Internet of Things,Big Data and other industries,people have higher requirements on network speed and stability.As a kind of channel coding technology,Low Density Parity Check codes with lower complexity and performance closes to the Shannon limit,which have achieved good results in practical applications of different communication scenarios.For LDPC codes of moderate length,non-binary codes can have better sparsity and decoding performance than binary formats(especially when the codes length is not very long),but the decoding(computation)complexity also higher than the binary LDPC codes.How to design a non-binary LDPC codes with good decoding effect and low complexity is one of the key issues in the research of LDPC codes.Based on the majority logic decoding algorithm and the non-binary LDPC codes,this paper proposes a method to improve the decoding performance.The main research work is divided into the following two aspects:1.In the LDPC codes decoding algorithms,the iterative hard reliability based on the MLGD algorithm has poor error correction performance.The essential reason is the hard information is used in the initialization and iterative process.For the problem of partial loss of information when the reliability is assigned during initialization,the error correction performance is improved by modifying the assignment of reliability at initialization.The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance.In addition,the IHRB-MLGD decoding algorithm adopts the hard decision mechanism in the iterative decoding process.The modified algorithm adds soft decision information in the iterative process,which improves the error correction performance while only slightly increasing the decoding complexity,and improves the reliability accumulation process makes the algorithm more stable.The simulation results show that the proposed algorithm has better decoding performance than the IHRB algorithm.2.Based on the proposed algorithm,the FPGA platform simulation implementation is given,and the practicability of the algorithm is verified.Based on the IHRB-MLGD algorithm,an improved decoding algorithm is proposed.The decoding algorithm with low hardware complexity and low performance loss is determined as the FPGA implementation of non-binary LDPC decoder.When the algorithm is implemented on the FPGA,after quantized the operations are simple.In this paper,the proposed decoding algorithm is used to implement the LDPC code coder and decoder on FPGA.The implementation results show that the decoder can achieve a better tradeoff between resource consumption and decoding throughput performance.