Design Of QC-LDPC Codes And Implementation Based On FPGA

In 1962, Gallager proposed LDPC codes; in 1996, the work of Mackay and Neal made the research of LDPC codes into a new phase. From then, the great performance of LDPC has been found gradually, and it has been proved that it can construct a kind of code the performance of which can approach Shannon limit. At present, LDPC has been applied into some fields, such as satellite communication, image transmission, digital watermark, mobile communication and so on.The construction of check matrix construction and codec algorithm of QC-LDPC is mainly researches in this dissertation, and some methods on those are introduced. The finite field and dual diagonal structure are combined to construct check matrix, which does not have four cycle and can implement rapid encoding. According to the characteristic of the check matrix, an overlapped semi-parallel decoder is come up with. On decoding algorithm, Min Sum algorithm is chose in this dissertation, which only contains comparison operation and add operation without multiply operation, and it takes an advantage of easy implementation.Based on the check matrix and codec algorithm above, QC-LDPC CODEC is implemented in FPGA chip, and the resource utilization is analyzed, at the same time, the data communication is implemented between PC and FPGA chip loaded with program. The entire structure of QC-LDPC CODEC is introduced, and every sub module is detailed. Meanwhile, the performance on iteration time-consuming of three decoding structure is compared: common semi-parallel decoding, overlapped semi-parallel decoding and full parallel decoding. Additionally, many data on the CODEC are examined. Based on the examination result, the error-correction performance is analyzed.