Research On LDPC Decoding And Implementation For 5G Terminal Simulator

The fifth generation of mobile communication technology(5G)is the main direction of current wireless communication development.The 5G terminal simulator is a communication simulation device based on the simulation and test technology of the air interface network side and terminal side in a broadband scenario,and is an indispensable test instrument in the process of the 5G construction.Low Density Parity Check(LDPC)codes shows excellent performance approaching to the Shannon limit,and in-depth research has been carried out in both coding and decoding.Therefore,LDPC has been widely applicated in the field of communication.Besides,The 3rd Generation Partnership Project(3GPP)has determined that the LDPC codes is the coding scheme of the data channel in the 5G enhanced Mobile Broadband(e MBB)scenario.This thesis studies the definition and structural characteristics of LDPC codes,introduces the coding and decoding process of 5G and research the construction method and coding scheme of 5G Quasi Cyslic-LDPC(QC-LDPC).This thesis based on message passing algorithms studies various classical decoding algorithms of LDPC codes,and analyzes the decoding performance and complexity of decoding algorithms.Simulation show that Offset Min Sum(OMS)and Normalized Min Sum(NMS)have better error correction performance when the correction factors are 0.5 and 0.8,respectively.The scheduling strategies of node messages in the process of LDPC decoding is studied.On this basis,this thesis proposes an LDPC decoding scheme that layered-based NMS algorithm for the 5G terminal simulator.And through fixed-point quantization,the bit width of the check node messages and variable node messages(or a posterior probability)is analyzed to have better decoding performance at 8bit and 10 bit,respectively.In the process of the design and implementation of decoder,this thesis proposed to store variable node messages and a posterior probability in the form of the message storage blocks according to the 5G LDPC codes base graph,and the size of the storage blocks are adjusted with the changing of the lifting factors.According to the change of the maximum degree of base graph,the number of updata units of variable node carried out in the storage block structure when the message is updata.For the check nodes,the check node messages of each layer are updated in parallel,and the number of check node update units is flexibly selected according to different lifting factors.The traditional decoder will store all the check node messages,however,in order to save storage resources,this thesis proposes that only one layer of check node messages storesed in the check node storage unit according to the layered structure.FPGA implementation of LDPC decoder using Verilog Hardware Description Language(HDL),the function and performance of the decoder are simulated and tested in conjunction with the Vivado and Modelsim simulation platforms.Implementation results on Xilinx chips show that attains a throughput of 278.19 Mbps and a latency of 36.92?s for 10 decoding iterations while Z=128.