Research And Implementation Of Low Complexity QC-LDPC Decoding Algorithm

As one of the important technologies to ensure communication reliability,channel error correction coding plays an important role in various communication systems.The variety of communication application scenarios also makes the channel coding patterns various.The LDPC code is one of the types of channel error correction coding whose performance is closest to the Shannon limit,and is applied in many scenarios such as optical fiber communication,deep space communication,and 5G.At the same time,the LDPC code is written into one of many communication standards as one of the standard patterns of the channel error correction code.However,in many communication standards,the LDPC code structure is generally recommended,but the LDPC code decoding algorithm and hardware implementation structure are not described in detail.Due to the structure of the LDPC code,the decoding mode and structure have a great influence on the complexity of the hardware implementation.Therefore,this paper studies and implements hardware from the perspective of reducing decoding complexity.The main contents are as follows.This paper first studies the construction method of LDPC code check matrix.In order to save hardware overhead,the QC-LDPC code which saves storage resources in hardware implementation is selected as the check matrix,and the QC-LDPC code check matrix is constructed by PEG algorithm,which effectively reduces the check matrix.The number of short loops ensures the decoding performance to some extent while saving hardware overhead.Secondly,the various decoding algorithms of LDPC codes are studied,and the performance of various algorithms is simulated and compared.The hardware implementation based on layered decoding algorithm is established.In order to reduce the complexity of hardware implementation,a pre-termination decoding scheme based on de-layering is designed,and the inter-layer deletion threshold is simulated and analyzed.When the verification module is saved in hardware implementation,PCE is also obtained and adopted.The performance of the hierarchical decoding algorithm of the verification method is similar.The complexity of the hardware structure implementation is analyzed,and the decoding process and overall structure are designed.Finally,the module design of the pre-terminated delete layered decoding structure is designed on the FPGA platform,and the functions of each module are designed and simulated to verify its function.The modules are cascaded,and the function verification of the designed decoder is completed on the development board,and the designed low complexity decoder structure is realized.