The QC-LDPC Encoder And Decoder Of Design

The LDPC code is created on the century60’s, it is the rise of a code which itsperformance is close to Shannon limit on the century90’s. At present, its encoding,decoding, performance testing theory is quite mature, in order to study the practicalapplication,now we force it on the implement of hardware. While the QC-LDPCcodes keep the error performance, because its quasi cyclic structure which makesthe code simply and it gradually become the preferred code in implementation ofhardware.For the construct of QC-LDPC codes are mostly based on Euclidean space andEG-LDPC code or even incomplete block of BIBD-LDPC code, the two code bothhave advantages. The main advantages of EG-LDPC code are code distance isrelatively large, and structure is flexible. In this paper, in order to highlight thedecoder which can handle code of great long LDPC code, and code of great weightLDPC code. Our constructed code based on spatial4599yards long, a length of4227LDPC code information. The code in the magnitude of of the error rate ofless than only1dB away from the Shannon limit.The advantage of QC-LDPC encoder compared to random LDPC codes is thesimple hardware implementation. This paper mainly introduces how to construct thegenerator matrix which has a quasi circulation form, and in accordance with theparallel, serial code gives three different encoder. Meanwhile illustrates the threeencoder structure of resource consumption and the coding speed in order to designmore encoder. Finally, FPGA implementation is applied with the serial encodingmethod.The main performance parameters of the decoder is throughput and bit errorrate, the FPGA should consider the consumption of resources. The paper introduce aminimum sum decoding algorithm based on the design of a parallel layer decodingstructure of the decoder, since the number of check node processor can be arbitrarilychosen.when the num of processor is8,the Decoding throughput can reach1.6Gbps.The gap of error rate performance diagram and the simulate is very small,the resource consumption is little. The hardware implementation of the FPGAplatform is XILINX XC5VLX155T, the software version is ISE14.4...