The Design Of12bit125MSPS Pipeline ADC

As the development of digital technique, the high speed and high precision A/Dconverters are becoming more and more important. Taking into account theadvantages of both speed and accuracy, the pipelined ADC is widely used in theWireless communications、High-definition digital TV、Active phased array radar, etc.The thesis presents designs a12Bit125MHz pipeline Analog-to-Digital Convert.Considering the speed、power consumption、area and dynamic characteristics. Thisdesigning adopts ten stages. Each leave of the first nine stages is1.5bit/stage. The laststage is a3Bit Flash ADC, and using the digital calibration techniques to improve theaccuracy of the ADC. The circuits include the S/H、high speed dynamic comparators、Sub-ADC、Sub-DAC、Clock and digital calibration circuit, etc. In order to obtainhigher gain and lower power consumption. The following technologies are taken:high-speed、high-gain telescopic architecture amplifier, the dynamic comparatorswhich are lack of kickback noise keep the low power consumption and improvedbootstrap sample switches used in S/H and MDAC, resulting in higher resolution andhigher linearity, the two-phase non-overlapping clock generator is designed to makethe circuits have a good performance in the high frequency. The layout is designed bythe soft of virtuoso.The ADC circuit is designed and validated by the soft of Cadence in Linux. Thischip is being manufactured in SMIC0.18μm six-metal CMOS mixed-signal process.The Simulation results show that the power dissipation is100mW with1.8v powersupply and the input range is-1V to1V. The ADC chip has12Bit resolution in125MHz sampling clock.