The ASIC Design Of Low Power And Scalable Fast Fourier Transformation

Digital signal processing due to its high accuracy, good flexibility, strong anti-interference ability and easy-to-large scale integration, etc., has replaced the traditional analog signal processing currently in many areas. DFT(Discrete Fourier Transform) plays a central role in a variety of digital signal processing, but due to the DFT has large amount of calculation and require considerable memory, it is difficult to achieve real-time processing so that limiting its application. Cooley and Tukey proposed the FFT(Fast Fourier Transform) algorithm in 1965 made the computation speed of DFT hundreds of times faster and solved the bottlenecks of implementation and application of digital signal processing,and therefore FFT processor became the most fundamental and important unit in digital signal processing. FFT has been widely used in digital communications, speech signal analysis, image processing, radar, seismic, biomedical engineering and other fields now.Because of the advantages of ASIC(application-specific integrated circuit) in power consumption, this project adopted the ASIC design method to design a FFT processor and it was designed to be scalable, which can be configured for 8 points, 16 points, 32 points, 64 Points, 128 points, 256 points, 512 points and 1024 points computation. This paper described the theory of Fast Fourier Transform theory, by comparing the complexity of the algorithm with different radix and the impact on power consumption, we used the DIT(Decimation-In-Time) and radix-2 algorithm to design the FFT processor. Then discussed the sequential structure, cascade structure, parallel structure and the array structure of common FFT hardware and this design chose the sequential structure according to the requirements of low power. A long-bit memory was divided into two short-bit memories and the number of real multiplications in butterfly was decreased from 4 to 3 to father reduce the power consumption. Through the discussion of the multiplier, we chose a modified Booth encoded multiplier. An effective address generation algorithm for this design was proposed in detail too. Pipeline structure was used between memory operation and butterfly computation to improve the computation speed. In addition, this paper describes the low-power methods in each stage of design.The Low Power and Scalable FFT processor was designed with Verilog HDL and functionally verified using Modelsim simulator. Xilinx FPGA was used for emulation. The design was synthesized, placed and routed using SMIC 0.18μm CMOS library. According to the need of our project, 8-256 points FFT processor was fulfill successfully by MPW((Multi Project Wafer). The simulation and test analysis showed that the calculation error of the FFT processor is less than 3% and there are 2063 clock cycles for 256 points FFT computation. At the 1.8V supply voltage, the average power consumption is about 1.17 mW/MHz. The FFT processor’s power, speed and accuracy have reached the desired goal.