The Design Of Low-Power Multipliers Based On Booth Algorithm

At the trends of diminishing nano-scale technology and higher integration chip technology, the power consumption of integrated circuits are drawing more attention of designer. This academic dissertation chooses the essential logic block of digital signal processor and microprocessor etc. for image and video processing——multipliers as the subjects of study. The project aims at two design issues of multipliers, speed and power dissipations. According as improved Booth algorithm's operation is fast parallel and adiabatic circuits can reduce the dynamic power consumption of circuits, this thesis proposes a new adiabatic multiplier structure based on improved booth algorithm. This multiplier is realized by CPAL (Complementary Pass-transistor Adiabatic Logic), and simulated on pre-layout and post-layout. Then, on the basis of techniques of reducing leakage power dissipations, we do some researches on the sub-circuits such as 1-bit full adder, 4-2 compressor and 4-bit carry lookahead adder etc. on technologies under 90nm. We try to apply a dual-threshold CMOS technique and a near-threshold technique into those adiabatic circuits, and compare with circuits that are not applied these techniques in terms of total power dissipations and leakage power dissipations. Finally, combining with the design idea of"PMOS transistor-based", this thesis proposes new logic (named 2P-2P2N) ultra low power circuits.This thesis mainly studies the design of low-power multipliers based on booth algorithm, and contains the main parts as follows:1. The theoretical basis and design tools referred are introduced. There are four sections: the improved booth algorithm, adiabatic circuits, techniques of reducing leakage power dissipations and design tools for IC.2. A design of four-phase adiabatic multipliers based on modified Booth algorithm is described. Not only does it propose a new adiabatic multiplier structure is also applicable to circuits based other adiabatic logic, but also described sub-circuits based on CPAL. In the end, improved booth multipliers based CPAL and conventional static CMOS logic are realized with technology TSMC 0.18μm, simulated on pre-layout and post-layout for logic verification and energy comparison, respectively. 3. Designs of adiabatic circuits adopting near-threshold techniques for reducing total power dissipations are introduced. The circuit characteristics of CPAL circuits applying near-threshold techniques are studied, choose the optimal low voltage, making logic function right and total dissipations lowest. Finally, 4-2 compressor is tested for verification.4. Designs of adiabatic circuits adopting dual-threshold CMOS techniques for reducing leakage power dissipations are introduced. According to the theory of dual-threshold CMOS techniques, critical and non-critical paths are found, and circuit characteristics of CPAL circuits applying dual-threshold CMOS techniques are studied. Finally, 1-bit full adder is tested for verification.5. A new adiabatic circuit is introduced. According as logic behavior of PMOS is contrary to that of NMOS and gate leakage current of PMOS is less than that of NMOS, we proposed new adiabatic logic 2P-2P2N ultra low power circuits. Finally, a combinational circuit 4-bit carry look ahead adder and a sequential circuit D flip-flop are all realized with this new logic.