Font Size: a A A

Research On Low-Power Multiplier Based On Power Gate Switched On In Sequence During A Single Cycle

Posted on:2022-02-19Degree:MasterType:Thesis
Country:ChinaCandidate:Y HaiFull Text:PDF
GTID:2518306512971389Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the continuous development of integrated circuit design technology and manufacturing process,speed and area is no longer a chip designers focus on the main factors.As the core component of microprocessor and digital signal processor,multiplier is widely used in the very low power fields such as Io T and implantable biochip.So the multiplier low-power design demand has important theoretical and practical significance.In this paper,a radix-16 Booth multiplier based on power gating is designed and implemented to solve the problem of high power consumption caused by glitch in low-power application scenarios.Firstly,the influence of glitch on the power consumption of multiplier under different scale,frequency and process conditions is analyzed.Secondly,the hardware structure and Unified Power Format description of each module of radix-16 Booth multiplier are designed.In the hardware design,as far as possible reuse high-power multiplicator,and adopt the way of concatation to reduce the area of the circuit,using power gating technology switched on in sequence to reduce the power consumption of the circuit,finally using UMC110 nm low-power process to implement logic synthesis.In order to verify the power reduction of the multiplier designed in this paper,Python scripting language was used to integrate the analog circuit simulation tool Ocean of Cadence Company to build a power test platform.The logic correctness of the multiplier was tested,and the static power and dynamic power of the power gating radix-16 Booth multiplier was analyzed.The analysis results show that the power consumption of the proposed power gating Radix-16 Booth multiplier is significantly lower than that of the existing unsigned multiplier in Design Ware library.The power consumption of the circuit is reduced by 23.94% at 100 MHz operating frequency,and the power consumption of the circuit is reduced by 41.28% at 20 MHz operating frequency.Under low-frequency operating conditions,the reduction effect of glitch power is more significant,which meets the requirements of design objectives.
Keywords/Search Tags:power gating, multiplier, switched on in sequence, Booth encoding
PDF Full Text Request
Related items