Based On 0.35¦Ìm Sige Technology, Low-power Complex Multiplier Asic Chip Design

With the rapid development of microelectronics technology, the technology ofdigital signal processing has been advancing greatly. Furthermore, power consumptionhas stood out, due to the developing trend of the portability and reliability, with especialconcern in the modem military renovation, where power capability and life span ofbattery can not meet the current demand under the situation that a soldier need tocommunicate, or to navigate by satellite. So the research of low-power architecture ofmicroprocessors has been an important project. In this background, the author engagedhimself in the research of the ASIC design of the low-power complex-numbermultiplier.After Analyzing the energy model of digital CMOS circuit, and researching thetypical low-power design method, the low-power design method and their efficiency atall level of the complex multiplier have been further discussed and the design flowreferred in this thesis has been put forward. In this thesis, emphasis is put on thelow-power design of the key unit multiplier, including the low-power design atarchitecture-level, circuit-level, transistor-level and physical layout-level. At last theverification of the processor and the implementation result of this low -power complexmultiplier with our own patent are given.The work in this dissertation can be concluded as following:The ASIC implementation of 16-bit low -power complex multiplier uses fullcustom and semi-custom method. The instruction set of this complex multiplier iscompatible with PDSP16X of ZARLINK.The final layout verification is successful andthe GDSII file can be tape out.Design a high-speed and low-power 16×16-b multiplier IP core with modifiedBooth encoders and Wallace Tree compressors. PG logic and Inverters are chosen toimplement most of the logic functions within our multiplier.This translates into thelower input gate capacitance and power dissipation as compared to the conventionalstatic CMOS without compromising their speed performance.The multiplier layout is designed using hand. According to process design rule and circuit parameters, the wire width, the contact figure and the wire direction arecomputed. Using low power layout method such as shareing the active area can makethe area and power of the chip smaller.Verification of complex-number multiplier includes pre-simulation, static timeanalysis, post-simulation and those are related to semi-custom and full-customsimulation method. The transistor-level netlist and RTL level testbench are runningcosimulations between NanoSim and VCS.The result of this dissertation can be described as following:1. It is a novel design of high-speed and low-power 16×16-b multiplier using0.35μm SiGe process. In order to achieve high-speed and low-power operation, mainlypass-gate (PG) logic circuits and full-custom designing method have been adopted.Results showed that the latency of the multiplier for the worst case is 4 ns at a supplyvoltage of 3.3 V, the average power dissipation is 7.78 mW at a frequency of 100MHzand the area of core is only 0.25 mm2. Comparing to the counter part from SynopsysDesign Ware Library the designed multiplier is about 38％faster and consumes 60％less power.2. A special DSP--complex multiplier is designed by using low power of differentlevel design methods and the standard desgin flow of SOC. The instruction set iscompatible with PDSP16X. The chip has 20000 gates and 120 pins. At a supply voltageof 3.3 V, 0.35μm SiGe technology, the maximal speed of the complex multiplier for theworst case is 125MHz and the average power dissipation is 74.5 mW@100MHz.