Research And Design On Low Power Floating-point Multiplier

With the development of Integrated Circuit Manufacture and Architecture design, processor design has been greatly improved. The time of System on Chip is coming. Multiplication is a fundamental operation in most arithmetic computing systems. Multiplier has large area, long latency and consumes considerable power. It becomes attractive how to optimize the design of multipliers from architecture, gate level, and physical design aspects.Based on the work in the design and development of floating-point multiplier in Godson-1 processor, this dissertation gives a systematic research on the every stages of multiplier considering delay, area and power consumption, and provides optimization method from architecture design aspect. The detailed research improvements are as followings.1. An improved Low Power Booth Encoder is proposed. Encoder is the foundation of quick multiplication arithmetic. The new encoder method is based on the research that how encoding will impact switching probability of multiplication circuit. It can decrease power consumption a lot by increasing delay and area a little comparing to conventional Booth Encoder.2. A new method of Dynamical Adjustment of Encoder according to the sequence of operator digital bits is provided. After analyzing the operators, it can choose the proper one from two operators to encode, so it can reduce the power consumption.3. A new Algorithm of Partial Products Reduction is given. Compared to existing algorithms, it can achieve global optimization of delay by taking into account the relationship between carry and sum; and unnecessary circuit switching is avoided by balancing the data path.4. A Floating-Point multiplier, supporting IEEE 754 Standard and full pipelined, is presented based on the research result of item1, 2, 3. A new Two-Way Multiplier architecture is proposed. It combines the traditional full-size architecture and half-size architecture, and can be dynamically adjusted according to different floating-multiplication instructions. It can reduce the delay of critical path of adder tree without increasing the area of multiplier according to full-size multiplier.5. A configurable fix-point multiplier is presented. Different architectures can be chosen according to different application fields. It is suitable to be integrated into configurable Intelligence Property core of processor.