Research And Application Of ASIC Design

The paper explores a design for 40/32bit multiplier circuit of high performance and high speed, which is used in high-performance F206 DSP chips. It mainly focuses on the multiply implementation by 2's complement algorithm, and has completed the functional emulation based on the hardware logic implementation.In this paper, the data format of DSP and basic float operations are discussed firstly in details, with the workflow of float multiply in emphasize. According to the comparison of several multiply algorithm in complement format, the thesis discusses the improved Booth algorithm and uses it in the multiplier design.The dissertation also elaborates the design theories for 40/32bit float/integer multiplier logic circuit. First, two typical Array multiplier structures are given, namely Iterative Array-IA and Wallace tree structure, and the method called improved two class pipeline Wallace tree structure, which mixed 4-2 compressors and full adders. And the paper makes further analysis in the structure. Then the paper introduces the function module design and measurability design of the multiplier, including Booth encoder, partial product producing logic and CPA circuit logic theory. After the comparison of carrying methods and structure of varied carry pass multiplier in common use, improved static Manchester and carry-skip method is used in the design of the high-speed carry chain. The paper even makes further analysis in the CMOS unit circuit operations and speed of the multiplier.On the basis of the hardware logic implementation, the multiplier is also described by the upside-down and form bottom to top methods. Finally, the complete logic simulation of the multiplier has been finished and logical integrated and validated by EDA software of Synopsys Series.