Design Of Multiplier IP Core For DSP

With the development of digital signal process technology such as image capturing,speech recognition et.al, the digital signal processor (DSP) plays more and more importantrole in practical application. DSP appears in cell phones, televisions or even limousine.Also with the maturity of process and technology, higher-performance，lower-price andmore stable DSPs are widely used in industrial control fields. As for DSPs, themultiplication operation is one of the most important operations. Therefore theperformance of multiplier directly determines the whole performance of DSPs. In DSPmultiplier design, delay time, operation speed, chip area and power dissipation should betook into consideration comprehensively. With the overall understanding of variousmultiplier architectures, modified Booth algorithm architecture is implemented in thismultiplier.In this paper, the basic principle of multiplier is introduced firstly, then severalmethods producing partial product and compressing partial product is included. Amongthem, the Booth algorithm and the modified Booth algorithm are derived and compared indetail. In modified Booth algorithm, even bits and its adjacent bit produce the partialproduct; therefore the number of partial products reduces in half. Moreover, the sign bit ofpartial compression product is discussed under the condition of signed multiplication andunsigned multiplication. On the circuit implement level, transmission gate andtransmission transistor are widely adopted to reduce chip area.The design is implemented in Chart0.35 BiCMOS process. A 16X16 multiplier isdesigned in both full-custom and half custom design flow. The logic verification is done byModelSim. Under Cadence IC 50 environment, the area of full-custom designed multiplieris 218842.72um2 while the half-custom designed one is 328764um2. Under the worst case,the power dissipation of full-custom designed multiplier is 8ns.