Design And Low Power Optimization Of Multiplier-accumulator For Digital Signal Processor

DSP multiplier-accumulator is the key unit in digital signal processing. One of the most important standards of DSP performance is the number of MAC operations in unit time.This paper mainly discusses the multiplier based on the digital signal processor optimized adder design, puts forward a new low-power circuit program, designed with a smaller overhead compression tree, completes 17 bits with a signed binary number multiplied by the compression process. This design uses the square root of the structure of mixed groups carry adder implementation, concludes with an effective structure to achieve universal signal digital processing of their required score model, zero detection, saturation overflow control and rounding operation. Booth encoding and the traditional performance comparison, sign extension with such a limited step of multiply-add operations carried out with the hybrid adder structure can improve the speed of the fastest 20%, hardware resources can reduce up to 37%. The frequency is up to 90MHz or more.We have been completed five kinds of technical optimization algorithms through theoretical analysis and synthesis of post-simulation experiments. These technologies improve the multiply-adder power consumption. Physical design and post-simulation experiments will show the low-power optimization has some effect.