The Design And Verification Of A YHFT-DX+ Multiplier Unit

With the rapid development of Digital Signal Processor, It is widely used in the fields of communication, signal prosessing multimedia and so on.With the expanding of application, higher performance is required for DSP. So it has more value on research and applications. This thesis takes the design of YHFT-DX+ multiplier unit for the background, researchs the high performance DSP and realizes YHFT-DX+ multiplier unit. The main contributions are as follows:Firstly, this paper analyzes the YHFT-DX+ multiplier unit functional requisitions and instruction types. The general architecture is prompted including three modules, three independent pipelines and a shared decoder.Secondly, the multiplier module has complex instructions and both 16-bit and 32-bit multiplication operation. The design of both 16-bit and 32-bit multiplication operation and hardware reuse is the key technology. A fast recursive multiplication algorithm is used in the design of 32-bit multiplication operation. And the design goal is achieved.Thirdly, in the design of multiplier module, the more research is on the multiplier. A glitch-free modified Booth algorithm is applied in the design. And the designed multiplier is improved and reduced power dissipation. The multiplier is on the key path of the multiplier module, which restricts the performence of the multiplier module. So the multiplier is designed by the method of full-custm. Part product producing and compressing are researched in the design. It gets a good result. Finite field multiplier is the key module of multiplier unit. So we made more research on it.We use the LSB semisystolic array algorithm in designing.Finally, it discusses the semi-custom of the YHFT-DX+ multiplier unit. The semi-custom of the multiplier unit technology is emphased on the place, routing and synthesize clock tree. The verification and the timing analysis are addressed at last.