Research Of Ternary Clocked Adiabatic Sequential Circuit

Multi-valued logic circuits can improve information carrying capacity of signal lines andinformation density of integrated circuits, which can solve the problems brought by manyinterconnect lines and the large area occupied by routing. Meanwhile, the adiabatic circuits canrecover and reuse energy effectively, thus greatly reducing the power consumption of the circuits.Therefore, by researching the structure and principle of multi-valued logic circuits and adiabaticcircuits, based on the theory of three essential circuit elements, a series of novel cross-stroageadiabatic circuits with double power clocks, ie, ternary clocked adiabatic sequential circuits, aredesigned, which can reduce the power consumption of the circuits and realize low powerconsumption for integrated circuits with high information density. The main contents of this paperare shown as follows:1、The theory of three essential circuit elements and design of ternary clocked adiabatic JKLflip-flop: Research on the theory of three essential circuit elements in-depth, ternary clockedadiabatic JKL flip-flop was designed based on this theory, and adiabatic novenary asynchronouscounter was design further.2、Design of ternary clocked adiabatic shift register: By studying ternary shift register,according to adiabatic calculation principle, ternary clocked adiabatic D flip-flop with the reset portand3-1multiplexer were derived to design firstly, and then the further design of ternary clockedadiabatic shift register was presented.3、Design of ternary clocked adiabatic synchronous reversible counter: By studying ternarysynchronous counter, energy recovery principle was introduced, ternary clocked adiabatic Dflip-flop with the reset port and the set port, reverse circulation gate and reverse circulation circuitwith the borrow function were derived to design firstly, and ternary clocked adiabatic synchronousreversible counter was proposed further.4、Design of ternary clocked adiabatic static random access memory (SRAM): By studyingternary SRAM, NMOS transistors with different thresholds were adopted, the row/column addressdecoder, storage cell, sense amplifier, read circuit, write cirucit and other basic circuits weredesigned based on DTCTGAL circuit, and ternary clocked adiabatic SRAM was designed further.5、Design of2-3mixed-valued/six-valued clocked adiabatic asynchronous up-down counter:By studying CTGAL circuit and DTCTGAL circuit,2-3mixed-valued/six-valued clockedadiabatic D flip-flop, shift right gate and carry/borrow circuit were derived to design firstly with mixed-valued coding technology, and then2-3mixed-valued/six-valued clocked adiabaticasynchronous up-down counter was realized further.The designed circuits were simulated by PSPICE to verify that these circuits have correctlogic function and characteristics of energy recovery. Compared to the traditional CMOS circuitswith the same function, the presented circuits have remarkable low power consumption.