Based On Standard Cmos Process, The Voltage-type Multi-valued Logic Circuit Design

The multiple-valued logic circuits have very strong advantages at increasing the signal amount taken in the signal wires, which provide an effective approach for solving the problems brought by the increase of the interconnection wires in the ICs. In order to realize the multilevel switch threshold in the voltage-mode multiple-valued logic circuits, the technique of ion implantation into the channel region of the MOSFET by controlling the impurity atoms has been applied in the previous literatures, which can not only increase the difficulty of the processing and the working procedure, but also increase the manufacturing cost. The multiple-input floating-gate MOSFET (Neuron MOSFET, abbr. neuMOS or vMOS) has the capability of weighted addition of all the input signals on the gate. It has been regarded as a more and more important technique, which bears the characteristics of strong unit transistor capability, and can realize threshold control under the standard CMOS processing conditions. In this thesis, based on the analyses of the device characteristics, the application of the neuMOS in the voltage-mode multiple-valued logic circuits has been researched.In this thesis, systematic analyses on the characteristics of the neuMOS have been elaborated, including the basic structure, the basic circuit, and the floating-gate gain factor, etc. By using the SPICE model of the neuMOS, the variable threshold characteristic has been researched deeply, and the variable threshold characteristic of the complementary structure has been analyzed emphatically, which provides a theoretic guidance for the design and application of the neuMOS in the multiple-valued logic circuits.Based on the switch-signal theory, the transportation calculation formulae have been built, which can describe the interaction relations among the neuMOS switch grid electrode input, transportation source and the circuit voltage threshold. The logic functions of every neuMOS have been all described in the formulae. Based on the above results, by using the neuMOS technique, the basic logic devices of the ternary logic circuits have been designed successfully.Furthermore, a static and dynamic voltage-mode CMOS ternary circuit design scheme similar to the DPL (Double Pass-Transistor Logic) structure has been presented. In this circuit structure, the two types of transistors - pMOS and nMOShave both been utilized, which can guarantee that the output signals have full logic swing and high noise margins.The design schemes in this thesis are all based on the standard CMOS processing techniques, which need not to modify the threshold voltage, and the structures are simple. The HSPICE simulation with the TSMC 0.35um double-polysilicon CMOS technique parameters has been implemented for the circuits designed. The many simulation results have verified the correctness of these design schemes.