Analysis And Research Of CMOS Adiabatic Logic And Power Clock Circuit

The operating principle and energy consumption of several typical CMOS adiabatic logic circuits are analyzed. Compared with other circuits, the ECRL circuit rejects the diode in the process of charging, and does not exist vacant flat problem for output of high and low voltage, so it is selected as key research circuit. Based on the analysis of the sources of the energy consumption, the defects of the ECRL circuits in energy recovery are discussed. When the voltage across the load capacitance is blow to threshold voltage of MOS transistor some left energy can not be recycled to the power clock, the circuit produces some of the non-adiabatic power. A new IECRL circuit structure is proposed, which achieves the recovery of non-adiabatic energy completely by using limited adiabatic losing energy. At the same time, a new structure of flip-flop based on IECRL is proposed, by adding a feedback path it samples and maintain the logic state of the output at the previous cycle, then the logic state of the output is feedback to the side of the input at the next cycle, so it achieves the logic function of the trigger. The simuation results prove that the trigger has made a certain degree of improvement in reducing the power dissipation compared with the ECRL trigger. Then we analyse the circuit structure of a four-phase sinusoidal power clock used for the adiabatic Logic, and make some of the optimization of its parameters.The Hspice simulation with 0.5 m BSIM3v3 model technology show that non-adiabatic consumption of ECRL circuit accounts for the major part of dynamic power consumption in low frequency (1Hz-40MHz) range. By adding the energy recovery path to achieve the effective recovery of non-adiabatic energy, compared with the ECRL, improved ECRL circuit (IECRL) reduces power consumption about 30.6%. Comparing with the existing flip-flops based on ECRL circuit, the new trigger based on IECRL has a slight consumption increase of RS flip-flop. Due to the application of the new feedback path, JK flip-flop omits the four inverter chain which is used to maintain the output state of the previous cycle, so the power consumption is reduced by about 50.9%. A designed four-phase sinusoidal power clock is realized, the phase of each level lag of 90 degrees compared with its previous level, and its own power is decreased by increasing frequency.