Extra low power, single clock power adiabatic circuit logic

Power dissipation is an important aspect of digital computing systems because of the increasing demand of portable systems such like lap top computers, cellular phones, personal digital assistant (PDA) and any kind of portable electrical digital system. The adiabatic circuit is a new approach to design of a low-power computer. Unlike conventional CMOS logic circuits, adiabatic circuits recover and reuse circuit energies that would otherwise be dissipated as heat and thus improve the portability of systems. The main inconvenience in implementing adiabatic logic is the necessity of using multi-power clock schemes, which is required for proper adiabatic operation and corrective functionalities in digital systems.; In this dissertation, the design of single power clock adiabatic circuits is considered. Two novel adiabatic circuits, which use the single power clock, are presented. The first adiabatic circuit, known as a single power Clock Adiabatic differential cascade voltage switch with Complementary Pass transistor Logic (CACPL), uses a back-to-back inverter structure as an adiabatic latch to hold the data properly and the complementary pass logic to provide a diode-free evaluation logic network. Analysis models and a synthesis procedure are used to optimize the design procedure. The implementation of a 4 x 4 parallel pipeline multiplier with an operating frequency of 35.714 MHz and power dissipation of 31.1 μW, demonstrates that the application of CACPL is in practice a lower power circuit.; The second configuration, known as a single power Clock Adiabatic Differential Pass-transistor Logic (CADPL), combines the area efficiency and power saving of ratioless, complementary pass-transistor circuits. The design of CADPL is discussed in a variety logic implementation and the average power dissipation can be determined using SPECTRE, a simulation program that is part of Cadence. A synthesis method is introduced for lower the delay of a CADPL network. The features of CADPL are then illustrated by comparing it with other adiabatic logic styles such as a 4-bit pipeline ripper carry adder and 4-bit pipeline carry lookahead adder designed by CMOS. Simulation results are provided to verify the functionality and power saving in the performance feature of CADPL.