Study On Critical Techniques Of Fractional-N PLL In Application Of UHF RFID Reader

UHF RFID technology becomes a hot research issue with the growth of Internet of Things, it's a preferred solution to replace traditional bar code identification technology because it has many advantage such as moderate identification distance without contact,bigger storage capacitance,better security,longer lifetime.This dissertation presents the research of fractional-N frequency synthesizer for UHF RFID reader ranging from specification plan,loop design to circuit and layout implement,several achievement has been acquired:First, based on requirements of different protocols on adjacent channel rejection of RX path and anti-jamming capability of TX path,frequency planning,phase noise and spur spec has been discussed.Second, the constant Kvco and constant sub-band distance VCO has been proposed to overcome variation of tuning gain of multi-band VCO. Post simulation illustrates that variation does not exceed14%and25%respectively.Third, an improved searching algorithm has been proposed to solve blind search area and low search accuracy in AFC. Calibration error has also been discussed.Forth, a low current mismatch charge pump based on dymaic biasing has been designed, current mismatch of which less than2%.Last, a fractional-N frequncy synthesizer in UHF RFID reader has been demonstrated in0.18μm BiCMOS process,which consume42mA from3.3V power supply.Post simulation illustrates that the settling time is no more than80us in the worst case, matlab simulation indicate that phase noise performance are-119.3dBc/Hz@300kHz,125.5dBc/Hz@500kHz and-129.3dBc/Hz@1MHz.This dissertation is supported by project "Research on short range monolithic RFID chip" under the Science and Development Fundation Project of ECNU (Porject No.782101020)...