Design Of Key Blocks Of Sigma-Delta Fractional-N Synthesizer

The design ofΣ-Δmodulation Franctional-N Synthesizer is based on the requirement of TD-SCDMA. We complete the design and simulation of the circuit (with Cadence spectre), as well as the layout and verification of the circuit (with Cadence virtuoso and Mentor calibre). The frequency of this synthesizer turns from 1830MHz to 1980MHz. The reference frequency is 19.68MHz.The design method of Top to Down is used, which is from the system level design ofΣ-Δmodulation Franctional-N Synthesizer to the transistor level design of each block. Firstly, the structures of each block are built according to the design requirement. Secondly, after each block's specification is decided, detailed design and simulation of these blocks are completed including Phase Frequency Detector (PFD), Charge Pump, Loop Filter (LPF) and Voltage Controlled Oscillator (VCO), then the loop parameters are optimized, each block have obtained the design specifications. Thirdly, the circuit consisted with the digital part is achieved. Finally, layout and verification of the circuit are completed in UMC 0.13um RF CMOS process.This paper is focused on the research of the PFD, the PFD is configured to separate the reset part and the delay part independently, the input signal edge data, which arrive during an added delay to remove dead-zone, are not lost and do not output the wrong information, resulting in faster locking property.Then, the standard of TD-SCDMA is introduced in this paper, with its requirements to the design of RF Local Oscillator.Once the design is accomplished, this frequency synthesizer can be applied to the TD-SCDMA base station and TD-SCDMA cell phone, and is instructive for the frequency synthesizer of the incoming 3G..