Delta-sigma Fractional-n Frequency Synthesizer, A Uhf Rfid Reader

Driven by the enormous market of UHF RFID, the research and development for Reader and Tag have grows explosively. The frequency synthesizer is the key block in Reader, and it is undoubtedly possible to integrate the frequency synthesizer into a chip with the development of CMOS process.Based on the protocols and spectrum regulations in UHF RFID, theoretical analysis and implement for Delta-Sigma Fractional-N frequency synthesizer of Reader are described detailedly in this thesis, and many creationary key techniques have been applied into the design of frequency synthesizer.Firstly, according to spectrum characteristics of transmitter and link parameters of receiver in UHF RFID, the specification of the frequency synthesizer has been analyzed systemically in Reader, and it has been proven correct by the system simulation model.Secondly, based on the RF parameters of Reader and the specification of the frequency synthesizer, the loop parameters and noise performance have been investigated systemically to guarantee that the loop characteristics can meet the noise requirements in the frequency synthesizer. The key design specifications such as loop bandwidth, VCO gain, Charge-pump current, Divider ratio and filter parameters have been specified on the condition of reasonable noise performance.Thirdly, the phase noise performance of VCO can be improved by applying the high Q-value taper spiral inductor. The taper spiral inductor can not only increase the Q-value of the resonator, improve the phase noise performance of VCO, but also decrease the die area.Fourthly, the symmetrical noise filtering technique has been brought forward and applied into the VCO design. It can avoid the noise mixing in tail current and power line in the N/PMOS complement cross-couple VCO. The measurement results show that this technique is useful.Fifthly, based on the error-feedback Delta-Sigma modulator, this thesis has brought out the technique of coefficient reconfiguring. It can adjust the pole freely when the loop parameters have been changed. It can improve the reliability against process variation and the successful probability for successful taping out.Sixthly, the technique of gain linearization based on synchronized compensation has been brought out in this thesis to solve the problem of gain variation during frequency adjusting, and this technique can greatly improve the loop stability.Finally, based on the specification of the frequency synthesizer, a Delta-Sigma Fractional-N frequency synthesizer applied into UHF RFID Reader has been designed for the first time. The measurement results indicate that this design can meet the requirement of the Reader system. This work has made a solid basis for the further research.