8ns 4M_bit High Reliability Of Static Random Access Memory

In order to meet the current high-capacity, high speed, high reliability, static random access memory (SRAM) and to solve more and more demand for high integration of SRAM yield problem by affecting the production process, the paper presents a 256k×16bit high-performance SRAM design. Mainly for two innovation described: First, in order to achieve high-speed requirements, we propose a new decoding structure. The high and low storage array sub-four sub-arrays. Data reading and writing, by the UB, LB signals to select the level of location choice. High and low eight bits of data simultaneously by four sub-arrays to be selected through two. The SRAM is used in a select array of eight, this will result in close to the output terminal and the output signal from the output at different times. The design of the coding structure to avoid such problems. Second, between the SRAM high integration, manufacturing process error-prone unit characteristics, designed to increase the redundancy logic and fuse (FUSE) to replace the error in SRAM cell, in order to improve yield. The 4M_bitSRAM chip SMIC0.18μm standard process. In each I / OPAD port hanging 50pF capacitor in the case to be simulated. Designed using 0.18um process with foreign similar products, this article SRAM access speed is only 8ns, operating temperature range of -55 ~ 125℃, while foreign products access speed 10 ~ 12ns, operating temperature range of -40 ~ 80℃. In power, the very design and foreign products, the dynamic current of 110mA, quiescent current of 5mA, only an increase in the area.