Design And Verification Of SRAM Self-detection Repair Based On ECC Circuit

In the space environment,a large number of radiation particles irradiate the memory chip,which results in Multiple Bit Upset(MBU)soft errors and Single Hard Error(SHE).Among them,hard errors will not be covered and eliminated.The accumulation of hard errors will inevitably affect the accuracy of data for memory with limited error correction ability.Therefore,in view of the two kinds of errors,it is of great practical significance to improve the self-detection and repair ability of memory.In this paper,the influence of single event multi-bit flip and hard error on memory is studied in depth.Based on the coding and decoding principle of low redundancy matrix-based codes,the circuit of low redundancy matrix-based codes which can harden 32-bit data and correct 4 adjacent errors is realized.The function simulation of the circuit is carried out and the error correction mode is analyzed.The method of judging type of error in memory cell by self-detection is studied.Based on the low redundancy matrix code circuit,the memory is hardened.The design of state controller is realized by finite state machine with the method of secondary detection.Thus,the function of repairing soft errors and judging the type of errors is realized.A fault injection platform is constructed to verify the correctness of the function of repairing soft errors and detecting hard errors.The method of repairing memory cell hard error is studied.By means of address mapping to isolate hard errors,a fault address analysis is designed and implemented,the state controller is improved,the functions of each circuit are coordinated,and the SRAM architecture for self-detection and repair of soft and hard errors is realized.Under the condition of SMIC 65 nm process,all circuits are synthesized,and the whole SRAM structure is verified by gate-level simulation.Finally,based on the AHB bus protocol,the system-level verification of design is carried out by using the bus function model.The AHB bus interface is designed for the SRAM structure of self-detecting and repairing soft and hard errors.The results show that the SRAM structure designed in this paper can be integrated into the system for application.