Research On Key Technologies Of 40nm High Speed SRAM Design

With the rapid development of science and technology,the requirements for the performance of integrated circuit chips are becoming much higher.However,the present memory fails to follow the acceleration of CPU,restricting the overall speed level of chips.As a mainstream Cache,studying with it is helpful to eliminate the gap of them.In this paper,high-speed SRAM is studied from three aspects:bit-cell,decoder and sense amplifier.In this paper,it makes a research on bit-cell size and analysis the influence of different PR&CR.Besides,researching on decoder is also contained,and it proved the advantage of 3/3 decoder by designed experiment.Following logical effort optimization method,the size of decoding circuit at all levels is further optimized,which significantly improves the decoding efficiency.Also in this paper,it study with SAEN,and aiming at the problem of amplification failure or high energy consumption caused by insufficient or excessive design margin,a novel SA with feedback structure and analog bit-line and word-line delay of replication memory cell is proposed.And the SA is turned on and off at the best timing,which effectively improves the stability and amplification efficiency of SRAM.Main contributions are as following:(1)Aiming at the failure of read and write in bit-cell design,the influence of different PR and CR on the power consumption and speed of memory cells is analyzed on the premise of satisfying the read-write constraints of bit-cells,so as to determine the CR and PR that meet the design requirements by building experimental circuit,using Virtuoso software of Cadence Company.And make experiments on this basis,further analysis of the impact of different transistor size on the performance of the storage,the final completion of the design of each transistor size of the cell array is completed.As the experiment shows,with the increase of the PR,the power of the units with different values shows a trend of first decreasing and then increasing,and the same trend appears on the speed comparison chart.The difference is that the former decreases more sharply,while the latter increases more sharply.With the overall analysis of speed and power consumption,it is concluded that the CR of the 40nm process used in this design is 1.2 and the PR is 0.6.And the experiment shows,with the increase of transistor size,the delay of cell array decreases and the energy consumption increases.By normalizing the two results,the pull-up MOS sides are 90/40 nm,the pull-down MOS are 180/40 nm and the access MOS are 150/40 nm.(2)According to the capacity requirement of 32K-bit,the overall storage array is divided into four sub-modules by using the storage array partitioning technology,and the overall layout of X128Y8D32 is determined.And for 128 lines,multilevel decoding is adopted to reduce the overall decoding time.For six-bit addresses,three different hierarchical structures are proposed:3/3 two-level decoder,2/2 two-level decoder,2/2 three-level decoder.The experimental circuit is built by Virtuoso software and simulated by Hspice software.And the simulation results show that in terms of speed,the 3/3 two-stage decoder is similar to the2/2/2 two-stage decoder structure,and the 2/2/2 three-stage decoder is the worst;in terms of power,the 3/3 two-stage decoder is the best,the 2/2 three-stage decoder is the second,and the 2/2 two-stage decoder is the worst.On this basis,the method of logical effort optimization is used.And the simulation shows that the decoder using the logic effort optimization method reduces the decoding delay by 50%compared with the decoder without this method.(3)In this paper,a novel self-sequential SA with replication cell array is proposed.Aiming at the problem that the artificial design of SAEN will fail to amplify or consume too much power due to insufficient or excessive margin addition,the replica bit-cell is used to simulate bit line and word line delay in order to trigger the rising edge of SA enabling signal and open the SA.With the feedback structure of the new SA,the amplified state is feedback,which triggers the descent edge of SA enabling signal and close the SA.Because of the opening and closing process of SA is not affected by artificial margin,it makes the SAEN more precise,to achieve the purpose of increasing speed and reducing power consumption.The simulation shows that,at the cost of increasing energy consumption by 30%,the speed was increased by 54.6%.Based on these researches,a high-speed SRAM with a capacity of 32K-bit is designed,which is based on 6T bit-cell structure with 40nm technology.Under the VDD=1.1V,25~oC and TT corner environment,the circuit is simulated with Spectre circuit simulation software of Cadence Company.And the simulation results show that the maximum CLK frequency of this high-speed SRAM can reach 1.67GHz,the reading power consumption is62.7uW/MHz,and the layout area is 170×120um~2.Compared with SRAM with the same process capacity generated by SRAM compiler,the CLK frequency is twice as fast,the power consumption is reduced by 6.7%,and the area is increased by 19.2%.Compared with the design requirements,the clock frequency increased by 11.3%.