Modeling And Design Of Fractional-N Frequency Synthesizers

Frequency synthesizers, which provide the up-conversion and down-conversion circuits with programmable local oscillator signals in transceivers, are the core modules in wireless communication systems. Thus, the performance of frequency synthesizers will influence the quality of wireless communication system directly. At present, phase-locked loop based frequency synthesizer is one of the most popular structures for frequency synthesizer implementation. Compared with conventional integer-N frequency synthesizers, fractional-N frequency synthesizers break the limitation of frequency resolution on loop bandwidth and can use higher input reference frequency. This has improved performance of frequency synthesizers in many aspects significantly. As a result, in recent years, fractional-N frequency synthesizers have been widely used.This paper starts from the basic work theories of phase-locked loop based frequency synthesizers, combining the work theories ofΣ-Δmodulators, totally analyzes and builds up both a linear model and a phase noise model forΣ-Δfractional-N phase-locked loops, and also discusses the mechanism of spur as well as the technologies for spur suppression. Then, aiming at the phase noise performance ofΣ-Δfractional-N phase-locked loops, the established model is applied to the concrete design of a phase-locked loop and the simulation results in MathCAD are given, too. At last, this paper illuminates the design principles and circuits implementation of a charge pump and VCO, both of which are the critical modules in phase-locked loops, in detail. Among them, the charge pump uses the circuit structure based on operational amplifier and the VCO uses the circuit structure based on cross-coupled negative resistance. Both circuits, which are designed, implemented, simulated and validated in the TSMC 0.18μm CMOS technology, achieve the expected performance requirements.