Charge-Pump PLL Z-domain Analysis And Low Noise Design

In recent decades, especially with the continuous improvement of integrated, PLL and microprocessor are widely used in the radio and frequency communications, and it has a very large market demand, low noise PLL. However, the PLL and a lot of analog, radio frequency integrated circuits will be interfered by digital circuits, especially the impact of interfering signals, which often interfere with the signal through the transmission of power and substrate. This effect will deteriorate lock loop performance, low-noise charge-pump phase-locked loop which makes the entire system on a chip design difficult. This paper discussed the design of low noise of each module and the elimination of non-ideal effects for the benefits of low noise.This paper described the working principle of charge-pump phase-locked loop and application, and then did the Z-domain analysis which gave the theoretical significance of this analysis, and compared with the previous derivation of the structure is simple. In the circuit simulation part, I eliminated the irrational effects of PFD / CP by adding delay and latch modules. This improved PFD eliminated the effects of CP's dead zone. The bias circuit of VCO is designed through the rational design and ring oscillator circuit which can achieve low noise results. In order to improve the speed of the voltage of VCO, the proposed circuit added a start-circuit which improved the locking speed. Then we can have a wider scope for design of the loop bandwidth, and also it helped to reduce the VCO phase noise. Finally we completed the layout design with the concern on the symmetry of the circuit design, matching problem, the design method of protection ring design, and a ESD protection circuit design.The designed PFD reset pulse width is less than 4ns which can eliminate the dead zone effect. There is a very good current matching slip of CP, and this structure is able to eliminate the clock feed-through, charge injection and other effects. Finally we got a VCO circuit which reached at a low noise: the center frequency is 216MHz and lock time is less than 2μs, the output frequency range of the circuit is between120MHz and operating voltage between 1.0 ~ 1.5V, the gain of VCO is 240MHz / V, and in the normal operating voltage range of phase noise is reduced to - 95.5 ~ -94dBc/Hz. The whole simulation process gives the PLL output jitter is less than locked 30ps.The results of Z-domain analysis for PLL and low noise design provided a good guide and reference value to us.