Design Of Single-event Transients Hardening And Low Jitter Phase-locked Loops

The Phase-Locked Loops(PLL) are applied extensively in data recovery,clockgenerator and frequency synchronizer fields.The PLL used in radiation environment isvery susceptible to the Single Event Transient Effect(SET)，which will make the PLL’sphase and frequency shift,or even induce to whole mircelectric system stop working.Forthe sake of the mircoelectric system can worknormally in the radiation environment,it isvery important and significative to study there inforcement technique on PLL. It isrevealed that the reinforcement technique on PLL will result in bad noiseperformance,making the jitter increase.Therefore it is an intractable problem to not onlyimprove the PLL’s ability to stand against the SET,but also keep its jitter performance.In response to these issues,this thesis presents the measures to optimize the PLLoutput noise,establishs the PLL’s Simulink model to analysis the SET affect andpresents the way to select the loop parameters, improves the radiation-hardenedtechnique for SET hardening and low jitter PLL design. The main work is as follows:(1) For the sake of optimizing the total output noise of PLL, this thesis analyses thecontribution of the different components of the PLL to the output phase noise and Spursources, presents the phase noise and Spur suppression measures. In order to ensure theintegrity of the Third Order Type II PLL anti-SET system analysis and reduce the loopparameters’ determination time, this paper establishes a PLL Simulink SET responseanalysis model, analyses the SET response situation at different loop parameters andfind the SET response trend to different loop parameters, present the measure todetermine loop parameters.(2) To improve the inhibition capability of the charge pump to noise and the SETeffect, to improve the stability of the system and reduce the sensitivity of the VCO tothe SET effect, this paper improved a voltage-charge pump and a three-order loopfilter.The combination of these two components can achieve the immunization of thecharge pump to the SET effect.Moreover,it improves a triple modular redundancy VCOstructure, in which0to VDD full voltage range of the oscillation can berealized.Comparing with the ordinary VCO,its Kvco gain reduces one half, therebyreducing the sensitivity of the output jitter to the control voltage and the SET effect.(3) To make the PLL’s simulation result close to the experimental result, themeasured noise is introduced in layout level simulation.In the typical situation,thedifference between the conventional simulation results of the Hspice and the chipmeasured results is about100ps. In order to verify the anti-SET PLL ability of thePLL,the SET effect simulation adopting the double exponential current source aremade.The heavy ion radiation experiment shows that the anti-SET and low Jitter PLL have a good jitter performance，the maximum cycle to cycle jitter is less than10%ofthe clock cycle.